#Field Programmable Gate Arrays
A field-programmable gate array is an integrated circuit designed to be configured by a customer or a designer after manufacturing – hence the term field-programmable.
#FPGA As A Channel-Emulator
Channel impairments such as Doppler, delay, link budget, and many others can be implemented on FPGA. Different FPGA-based development boards can be chosen to emulate the delay and Doppler effects from Xilinx such as Zynq UltraScale RFSoC family which integrates the key subsystems for multiband, multi-mode cellular radios into an SoC platform that contains an Arm-based processing system. In addition to the channel emulation use-case, FPGA boards can be used as an accelerator by offloading processing hungry tasks within the physical layer from the Intel-based processors to FPGAs. Accordingly, the processing is distributed and could be load-balanced among the processing units and the FPGA boards, where the interconnection between them can be through any of the standard interfaces like PCIe, Ethernet, etc. On the other hand, FPGAs that are located inside the SDRs can be utilized to perform part of the Physical layer functions which could be low-phy or high-phy. As a consequence, no need for an additional FPGA board if its resources, number of logic cells, block RAM size, DSP blocks etc, are satisfying the requirements of the offloaded task.
#NTN Channel-Emulator configuration
The NTN channel emulator, a core component for verifying and validating the NTN development, has been implemented on top of a field-programmable gate array (FPGA) using custom-designed hardware from VadaTech. It provides an IP-Core implementing the RTT delay using a deep first in first out (FIFO) buffer, which utilizes an external Double Data Rate (DDR) Synchronous Dynamic Random-Access Memory (SDRAM) chipset. The implemented delay length is based on the frequency rate at which the data writes and reads to/from the Deep FIFO, and the depth of the FIFO buffer. By fixing the depth of the FIFO buffer and manipulating the frequency of the sample generation, which then are passed through the Deep FIFO, we are able to emulate various delays, reaching RTT values of up to 600 ms.